WAVE537 - Dual-CORE decoder HW IP-ip-21864

¥10,000.00
有货
SKU
ip-21864
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供应商 Chips&Media
型号 Dual-CORE HEVC, AV1 & H.264, AVS2, VP9 combined decoder HW IP
类型 Soft IP
到期日 Available on request
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特征 HEVC/H.265 Main Profile @L5.1 AVC/H.264 BP/CBP/MP/HP Profile @L5.2 AV1 Main Profile @L5.1 VP9 Profile 0/Profile 2 (HBD) @L5.1 AVS2 Main 10 Profile @L8.0.60 Performance: 4K120fps, 8K30fps, 8K60fps Bus interface: A 32-bit APB bus and 128-bit AMBA3 AXI buses (w/ additional secondary AXI) 50~60% bandwidth saving while decoding process by reference frame compression Multi-instance handling for multi-channel decoding Configurability for codec standard and customizable features
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WAVE537 is a HEVC/H.265, AVC/H.264, VP9, AVS2, and AV1 decoder IP developed by Chips&Media. This IP core is designed and architected to support real-time video decoding up to 8K60fps with a dual-core. For HEVC/H.265 and AV1, this IP can decode up to 8K60fps with a dual-core and decode up to 4K60fps with a single-core for AVC/H.264, AVS2, and VP9. WAVE537 is highly optimized for memory bandwidth loading and power management. A specialized hardware block called CFrame is integrated into the video IP. With compression of reconstructed frames for future reference, WAVE537 can significantly reduce bus bandwidth by 50% on average while accessing frame data effectively in the external memory. It is easy to integrate into SoC since it can be connected through industry-standard interfaces, 32-bit AMBA3 APB bus for host CPU system control, and 128-bit AMBA3 AXI for data transfer. Two 128-bit AXI buses are available for VPU: one for accessing external memory and the other for on-chip SRAM memory. The WAVE537 is suitable for applications across various industry segments, including ultra-high-definition televisions (UHDTVs), wearable devices, set-top boxes(STBs), VR·ARs, smartphones, tablets, data server,s, automotive, IP cam/surveillance, driving recorders, infotainments, and any others with super-high resolution.

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