The ARM VSL240 PHY is suitable for both Host and Device applications within a Serial ATA system. The VSL240 PHY operates to the Serial ATA specification using either a 10-bit or 20-bit interface to a SATA Link Layer. Recovered data is provided using SATA compliant D-word alignment. The VSL240 provides a comprehensive feature set, a well-defined architecture, and a roadmap to future products. The VSL240 is is available and silicon proven in TSMC 90G, 90GT, 90G-OD, and IBM/Chartered 9SF. The VSL240 PHY is comprised of a hardened GDSII Physical Medium Attachment (PMA) sublayer containing the SerDes, plus a soft Physical Coding Sublayer (PCS) Verilog module that is connected to the hard macro at the PMA interface. The PCS, when coupled with the hardened PMA SerDes macro, provides a Serial ATA PHY with compliant signals for the end customer. Since the VSL PHY family includes many test features and capabilities that are not part of the Serial ATA specification, additional pins from the PMA layer are also available. The feature set for the ARM VSL240 PHY includes: * Serial ATA II Revision 2.6 compliant * Gen1i, Gen1m, Gen1x, Gen2i, Gen2m and Gen2x compliant * Initialization and power saving modes * Full +/- 5700 ppm data tracking capability in all modes * Transmission jitter generation and receiver jitter tolerance which exceed Serial ATA jitter specifications * 10 or 20 bit interface (build option) * Serial ATA compliant command and status signals * K28.5 comma detection * ALIGN detection and alignment * Selectable lane polarity inversion * Host or Device applications * Programmable serial transmit amplitude * Programmable serial receiver equalization * Status pins for checking PHY functionality * Integrated bandgap * Automatic driver/receiver impedance calibration * Very small size * Extensive built in testability * At-speed BIST circuitry with various PRBS and 8B10B patterns * Multiplexed scan for testability of all digital logic * Eye width mapping and on-chip jitter generation capability * Multiple loop back modes * Serial Control Register * Support for DC and AC JTAG (IEEE1149.1 and 1149.6 EXTEST) The ARM VSL240 PMA sublayer consists of one or more Lane Blocks that perform the parallel-toserial and serial-to-parallel conversion for a physical layer interface, and a Common Block which provides clocks and bias. See the functional block diagram in Figure 2-1, which shows an example of a four lane PHY. The user can choose to have one, two or four lanes in a single PHY. Each transmit section of a Lane consists of an 10- or 20-bit Serial ATA interface, a serializer, a differential CML driver with selectable de-emphasis and swing levels, and a BIST pattern generator. Each receive section of a Lane consists of a differential CML receiver with equalization, clock and data recovery circuitry, signal detection, de-serializer, comma (K28.5) detection and word alignment, 10- or 20-bit Serial ATA interface, elastic buffer and BIST pattern verifier. The Common Block generates all required bias currents, contains startup and auto calibration logic, and contains the PLL which multiplies the reference clock to the required serial link rate and provides the reference clock for each of the Clock/Data Recovery (CDR) units. The VSL240 is provided in standard x1, x2, x4, x8, and x16 lane configurations with support for both wirebond and flip chip packages for easy integration into a variety of designs.