The ARM VSL230 PHY is fully compliant with the CEI-6GSR and XAUI standards and is suitable for applications with data rates from 1.06G to 6.4G. The VSL230 provides a comprehensive feature set, a well-defined architecture, and a roadmap to future products. Additionally, the VSL230 has outstanding jitter performance and includes powerful TX and RX equalization for excellent performance over long backplanes. The VSL230 is available and silicon proven in TSMC 90G, 90GT, 90G-OD, and Chartered 9SF. The VSL230 PHY is provided as a hardened GDSII Macro containing the SerDes. The feature set for the ARM VSL230 PHY includes: * CEI-6GSR Compliant, CEI-6GLR compatible * Compliant with XAUI, CX4 and KX4 standards and compatible with SRIO * Transmission jitter generation and receiver jitter tolerance which greatly exceed XAUI specifications * Programmable driver amplitude * Programmable pre-cursor and post-cursor pre-emphasis * Programmable receiver equalization * 8 bit, 10 bit, 16 bit or 20 bit interface * Signal Detection with selectable threshold * Multiple power saving modes * Status pins for checking PHY functionality * Integrated bandgap * Automatic driver/receiver impedance calibration * Very small size * Extensive built in testability * At-speed BIST circuitry with various PRBS and 8B10B patterns * Multiplexed scan for testability of all digital logic * Eye width mapping and on-chip jitter generation capability * Multiple loop back modes * Serial Control Register * Support for DC and AC JTAG (IEEE1149.1 and 1149.6 EXTEST) The ARM VSL230 PHY consists of one or more Lane Blocks that perform the parallel-to serial and serial-to-parallel conversion for a physical layer interface, and a Common Block which provides clocks and bias. The user can choose to have from one to sixteen lanes in a single PHY. Each transmit section of a Lane consists of an 8-bit, 10-bit, 16-bit or 20-bit parallel interface, a differential CML driver with selectable de-emphasis and swing levels, and a BIST pattern generator. Each receive section of a Lane consists of a differential CML receiver with programmable equalization, clock and data recovery circuitry, signal detection, de-serializer, 8-bit, 10-bit, 16-bit or 20-bit parallel interface and BIST pattern verifier. The Common Block generates all required bias currents, contains startup and auto calibration logic, and contains the PLL which multiplies the reference clock to the required serial link rate and provides the reference clock for each of the Clock/Data Recovery (CDR) units. The VSL230 is provided in standard x1, x2, x4, x8, and x16 lane configurations with support for both wirebond and flip chip packages for easy integration into a variety of designs.