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| 供应商 | Arm |
|---|---|
| 型号 | VSL220 PHY for XAUI and related applications. Designed for 90nm processes. |
| 类型 | Hard IP |
| 到期日 | Silicon proven |
| 源网址 | View more |
| 特征 | Meets or exceeds XAUI specifications Excellent jitter performance exceeds specifications for transmit jitter and receiver jitter tolerance Very small size with low power consumption Programmable driver amplitude control with multiple pre-emphasis levels Programmable receiver equalization Extensive power-down modes Integrated BIST with multiple patterns and loopback modes Automatic input/output impedance calibration Simple parallel interface with individual, per -lane controllability Hot swappable/pluggable |
| 详情页 | View more |
| 附件链接 | View more |
The ARM VSL220 PHY is fully compliant with the XAUI standard and is suitable for many applications requiring data rates ranging from 1.06G to 3.2G. The VSL220 PHY provides a comprehensive feature set, a well-defined architecture, and a roadmap to future products. Additionally, the VSL220 PHY includes powerful transmit and receive equalization for excellent performance over long backplanes. The VSL220 is available and silicon proven in TSMC 90G, 90GT, 90G-OD, and IBM/Chartered 9SF. The VSL220 PHY is provided as a hardened GDSII Macro containing the SerDes. The feature set for the ARM VSL220 PHY includes: * Compliant with XAUI, CX4 and KX4 standards and compatible with SRIO * Transmission jitter generation and receiver jitter tolerance which greatly exceed XAUI specifications * Programmable driver amplitude and pre-emphasis * Programmable receiver equalization * 8 bit, 10 bit, 16 bit or 20 bit interface * Signal Detection with selectable threshold * Multiple power saving modes * Status pins for checking PHY functionality * Integrated bandgap * Automatic driver/receiver impedance calibration * Very small size * Extensive built in testability * At-speed BIST circuitry with various PRBS and 8B10B patterns * Multiplexed scan for testability of all digital logic * Eye width mapping and on-chip jitter generation capability * Multiple loop back modes * Serial Control Register * Support for DC and AC JTAG (IEEE1149.1 and 1149.6 EXTEST) The ARM VSL220 consists of one or more Lane Blocks that perform the parallel-to serial and serial-to-parallel conversion for a physical layer interface, and a Common Block which provides clocks and bias. The user can choose to have from one to sixteen lanes in a single PHY. Each transmit section of a Lane consists of an 8-bit, 10-bit, 16-bit or 20-bit parallel interface, a differential CML driver with selectable de-emphasis and swing levels, and a BIST pattern generator. Each receive section of a Lane consists of a differential CML receiver with programmable equalization, clock and data recovery circuitry, signal detection, de-serializer, 8-bit, 10-bit, 16-bit or 20-bit parallel interface and BIST pattern verifier. The Common Block generates all required bias currents, contains startup and auto calibration logic, and contains the PLL which multiplies the reference clock to the required serial link rate and provides the reference clock for each of the Clock/Data Recovery (CDR) units.
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