The ARM VSL210 PCI Express Serial Link PHY is a member of the Velocity 200 PHY Series. The VSL210 provides a complete PCI Express Gen 1 PHY that is compatible with the PCI Express Base 1.0a/1.1 specification with PIPE interface (rev 1.90). It offers exceptionally good jitter performance, low power consumption, and extensive testability within a small physical size. The VSL210 is available and silicon proven in TSMC 90G, 90GT, 90G-OD, and IBM/Chartered 9SF. The ARM VSL210 PHY is suitable for both Root Complex and End Point applications within a PCI Express system. The VSL210 PHY provides a comprehensive feature set, a well-defined architecture that allows designers extensive flexibility for various applications, and a roadmap to future products. Additionally, the VSL210 PHY provides support for a number of PCI Express addendums and extensions including the Mobile Graphics Low Power addendum and the Wireless Form Factor extension. The VSL210 PHY is comprised of a hardened GDSII Physical Medium Attachment (PMA) sublayer containing the SerDes, plus a soft Physical Coding Sublayer (PCS) Verilog module with a PHY Interface for the PCI Express (PIPE) that is connected to the hard macro at the PMA interface. The PIPE PCS, when coupled with the hardened PMA SerDes macro, provides a PCI Express PHY with PIPE compliant signals for the end customer. Since the VSL PHY family includes many test features and capabilities that are not part of the PIPE, additional pins from the PMA layer are also available. The feature set for the ARM VSL210 PHY includes: PCI Express Gen 1 compliant Supports 2.5 Gbps data rate Root Complex or End Point applications Root Complex supports Port Bifurcation factors of x1, x4, or x8 Transmission jitter generation and receiver jitter tolerance which exceed PCI Express jitter specifications Electrical Idle signaling and detection Receiver detection 8B10B encode/decode, comma detection and symbol alignment Supports various PCI Express modes and extensions Power saving (P0, P0s, P1, P2) and Low Signal Swing modes Clock Power Management Wireless Form Factor Programmable amplitude and pre-emphasis Programmable receiver equalization PIPE v1.90 compliant signals 8 bit or 16 bit interface (build option) Status pins for checking PHY functionality Integrated bandgap Automatic driver/receiver impedance calibration Very small size Extensive built in testability At-speed BIST circuitry with the PCI Express compliance pattern, plus various PRBS and 8B10B patterns Multiplexed scan for testability of all digital logic Eye width mapping and on-chip jitter generation capability Loop back modes Serial Control Register Support for DC and AC JTAG (IEEE1149.1 and 1149.6 EXTEST) The ARM VSL210 PMA sublayer consists of one or more Lane Blocks that perform the parallel-to serial and serial-to-parallel conversion for a physical layer interface, and a Common Block which provides clocks and bias. The user can choose to have from one to sixteen lanes in a single PHY. Each transmit section of a Lane with associated PIPE logic consists of an 8- or 16-bit parallel interface, an 8B10B encoder, a serializer, a differential CML driver with selectable PCI Express de-emphasis and swing levels, and a BIST pattern generator. Each receive section of a Lane with associated PIPE logic consists of a differential CML receiver with equalization, clock and data recovery circuitry, signal detection, de-serializer, comma (K28.5) detection and word symbol alignment, 8B10B decoder, 8- or 16-bit parallel interface, elastic buffer and BIST pattern verifier. The Common Block generates all required bias currents, contains startup and auto calibration logic, and contains the PLL which multiplies the reference clock to the required serial link rate and provides the reference clock for each of the Clock/Data Recovery (CDR) units. The VSL210 is provided in standard x1, x2, x4, x8, and x16 lane configurations with support for both wirebond and flip chip packages for easy integration into a variety of PCI Express designs.