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供应商	Arasan Chip Systems
型号	VESA DSC V1.2 Encoder
类型	Soft IP
到期日	Silicon proven
源网址	View more
特征	Fully compliant with the VESA DSC 1.2 standard Capable of decoding up to 4K video at 30fps in FPGA and 8K video at 30fps in ASIC applications Three clock domains Stream and APB clocks operate the applicable interfaces Independent decoder clock runs the core functions Uses synchronous design techniques and a technology abstraction layer for internal SRAM buffers Completely pipelined; can be stalled as necessary to properly manage input and output rates
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附件链接	View more

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详情

The Arasan’s VESA DSC v1.2 Encoder IP core compresses high-definition streams in real time at resolutions ranging from 480 to 8K. The core supports 8, 10, 12, 14 or 16 bits per pixel in RGB or YCbCr format (4:4:4 or 4:2:2). The DSC Encoder core is industry-standard in its integration of host setup and control, data input, and visual output. Arasan’s VESA DSC Encoder IP is seamlessly integrated with Arasan’s DSI Tx IP. Arasan’s expertise is backed by our unique silicon-proven design discipline and product development process that ensures fast silicon success with our analog and digital IP. Offered as a Total IP solution including RTL Host Controller IP, Verification IP, Software Stack, and Hardware Development Platform

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