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| 供应商 | T2M |
|---|---|
| 型号 | USB 3.1 Type-C PHY IP, Silicon Proven in UMC 55SP/EF |
| 类型 | Soft IP |
| 到期日 | Silicon proven |
| 源网址 | View more |
| 特征 | Support half rate mode (5Gbps) and full rate mode (10Gbps) Tolerate max +/-7000ppm input frequency offset 32bit/40bit selectable parallel data bus Programmable transmit amplitude 3 taps/2 taps selectable FFE Receiver CTLE and One-tap perspective DFE Build in self-test with PRBS7/31 pattern generation and checker for production test Integrated on-die termination resistors Support receiver detection Support LFPS signal generation and detection |
| 详情页 | View more |
| 附件链接 | View more |
A high performance, high-speed SERDES IP called USB3.1Type-C PHY is created for semiconductors that provide high bandwidth data connection while using less power. A specific design for USB 3.1 type-C applications is the USB 3.1Type-C PHY IP. A dedicated PCS can be provided together with the USB 3.1 Type C PHY IP to complete functionality of various applications, including elastic buffer, scramble/de-scramble, data encoding/decoding, PRBS generation/checking, registers control and testing. Depending on the customer's choice, PCS is offered as either a hard or soft macro; additionally, the PCS specification will be made available separately. Using a test bench constructed in Verilog HDL, the NC-Verilog simulation software verifies PHY functionality.
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