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供应商	T2M
型号	USB 3.1 Type-C PHY IP, Silicon Proven in SMIC 14SF+
类型	Soft IP
到期日	Silicon proven
源网址	View more
特征	Support half rate mode (5Gbps) and full rate mode (10Gbps) Tolerate max +/-7000ppm input frequency offset 32bit/40bit selectable parallel data bus Programmable transmit amplitude 3 taps/2 taps selectable FFE Receiver CTLE and One-tap perspective DFE Build in self-test with PRBS7/31 pattern generation and checker for production test Integrated on-die termination resistors Support receiver detection Support LFPS signal generation and detection
详情页	View more
附件链接	View more

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详情

The USB3.1Type-C PHY is a high-performance, high-speed SERDES IP designed for semiconductors that support low-power, high-bandwidth data transfers. The USB 3.1Type-C PHY IP is a particular design for USB 3.1 type-C applications. To fulfil the functionality of various applications, such as elastic buffer, scramble/de-scramble, data encoding/decoding, PRBS generation checking, registers control, and testing, a separate PCS can be offered in addition to the USB 3.1 Type C PHY IP. PCS is available as a hard macro or a soft macro, depending on the customer's need. Additionally, the PCS standard will be made independently accessible. The NC-Verilog simulation program validates PHY functionality using a test bench developed in Verilog HDL.

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