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| 供应商 | T2M |
|---|---|
| 型号 | USB 2.0 PHY IP, Silicon Proven in SMIC 12SF++ |
| 类型 | Soft IP |
| 到期日 | Silicon proven |
| 源网址 | View more |
| 特征 | Compliant with USB2.0 and USB1.1 specification Compliant with UTMI Specification Version level 3. Supports HS(480Mbps)/FS(12Mbps) /LS(1.5Mbps) modes All required terminations, including 1.5Kohm pullup on DP and DM, and 15Kohm pull-down on DP and DM are internal to chip 16-bit, 30MHz or 8-bit, 60MHz parallel interface for HS/FS Serializing for transmitting data stream and Deserializing for receiving data stream USB Data Recovery and Clock Recovery on receiving Integrated Bit Stuffing and NRZI encoding for Transmit Integrated Bit Un-Stuffing and NRZI decoding for Receive SYNC and EOP generation on transmit packets and detection on receive packets |
| 详情页 | View more |
| 附件链接 | View more |
A full physical layer (PHY) IP solution designed for outstanding performance and minimal power consumption is the USB2.0 PHY IP. The USB2.0 IP implements the High-Speed USB 2.0 transceiver, which can be used with hosts, devices, or OTG function controllers. The USB2.0 PHY IP, which supports both Full-Speed (12 Mbps) and Low-Speed (1.5 Mbps) data rates, comes after the UTMI+ level 3 specification. 480Mbps of high-speed data can be transferred by combining numerous mixed-signal circuits. The enhanced USB Battery Charging standards, which are designed for mobile and consumer product applications, are also supported by the USB2.0 PHY IP. Small chip size and low power consumption of the USB2.0 PHY IP transceiver did not compromise performance or data throughput. The USB2.0 PHY IP contains a full on-chip physical transceiver solution with Electrostatic Discharge (ESD) protection, a clock generating block provided by an internal PLL, and a resistor termination calibration circuit in order to fully enable host and device functionality.
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