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| 供应商 | Cadence |
|---|---|
| 型号 | Proven PHY IP for USB Device, Host, and OTG with small footprint and low active power |
| 类型 | Hard IP |
| 到期日 | Silicon proven |
| 源网址 | View more |
| 特征 | Compliant with USB 2.0 specification and backwards compatible to USB 1.1 specifications Supports host, peripherals, and OTG applications Supports Battery Charging Specification v1.2 Supports link power management (LPM) Comprehensive test features: datapath loop back, scan, BIST, bypass 8-bit 60MHz and 16-bit 30MHz parallel interfaces APB and JTAG interfaces Multiple reference clock supported from 9.6MHz up to 52MHz |
| 详情页 | View more |
| 附件链接 | View more |
The ubiquity of USB 2.0 in devices makes it nearly mandatory for any USB connectivity solution. The utility of USB 2.0 allows devices to have small buffers even at high data rates, supporting efficient device connection for smaller data sets in applications ranging from the mobile and consumer market, to enterprise, automotive, and internet of things (IoT). The Cadence? PHY IP for USB 2.0 for TSMC is designed to the USB 2.0 specification, and operates at High Speed (480Mbps), Full Speed (12Mbps), and Low Speed (1.5Mbps). The PHY IP complies with the UTMI v1.05 specification. The PHY IP also supports the USB Battery Charging Specification, Revision 1.2. The PHY IP is architected to quickly and easily integrate into any system on chip (SoC), and to connect seamlessly to a Cadence or third-party UTMI-compliant controller. Implemented on various process technologies, the PHY IP provides a cost-effective, low-power solution for demanding applications. It offers SoC integrators the advanced capabilities and support that not only meet, but exceed the requirements of high-performance designs and implementations. The PHY IP is silicon proven, and has been extensively validated with multiple hardware platforms. Cadence offers a comprehensive IP solution that is in volume production, and has been successfully implemented in more than 400 applications.
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