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UHT-JPEG-E, Ultra High Throughput JPEG Encoder-ip-21843
￥10,000.00
| 供应商 | ALMA Technologies |
|---|---|
| 型号 | Up to 32 samples per clock cycle, 8/10/12-bit per component and CBR Motion JPEG video rate control encoding |
| 类型 | Soft IP |
| 到期日 | Silicon proven |
| 源网址 | View more |
| 特征 | Ultra high throughput in low-end silicon with full ITU T.81 compliance 4:4:4, 4:2:2, 4:2:0 and 4:0:0 (grayscale) raster scan image or video input 8-, 10- and 12-bit per component sample depth encoding Up to 32 samples per clock cycle encoding, using scalable and transparent parallel processing Single - multiple pixels - raster scan interleaved input and single, ready-to-use, JPEG byte stream output Programmable Quality Factor, or constant bitrate video encoding On-the-fly video bitrate changes supported Algorithmic encoding latency of approximately 32 scan lines for 4:2:0 and 16 scan lines for all other sampling formats Configurable full on-chip or mixed on/off-chip memories implementation CPU-less, complete and standalone operation |
| 详情页 | View more |
| 附件链接 | View more |
The UHT-JPEG-E core from Alma Technologies is a very high performance 8-bit Baseline and 12-bit Extended JPEG encoder, designed to enable the massive pixel rates of 4K/8K resolutions, as well as the ultra-high frame rate video applications, in highly cost-effective FPGA and ASIC implementations.
The encoder is fully compliant to the ITU T.81 specification and supports encoding of 4:4:4, 4:2:2, 4:2:0 and 4:0:0 (grayscale) images or video streams, in 8-, 10- or 12-bit per component sample depths. The UHT-JPEG-E can be implemented using only on-chip memory resources, while using off-chip memory too is also natively supported. Designed with a user configurable architecture, the encoder scales to offer a sustained encoding throughput from 1 to 32 samples per clock cycle.
Using multiple internal processing engines, the UHT-JPEG-E core offers the needed performance through its scalable parallel architecture. Each input image or video frame is split internally into chunks and each chunk is assigned to one of multiple internal compression units. This is done in a way which is totally transparent to the system utilizing the IP, abstracting all the parallelization complexity from the rest SoC components. The number of internal compression units is configurable before synthesis, adapting to the implementation technology speed, and non-critical resources are shared between the multiple compression engines.
The UHT-JPEG-E uses a single uncompressed data input interface - accepting raster scan pixels - and produces a single, ready-to-use and fully compliant JPEG stream output. The UHT-JPEG-E employs also a constant bitrate video encoding option, supporting the bandwidth or storage constrained Motion JPEG video applications. Its operation is completely standalone, without needing any host CPU or GPU power. The output JPEG byte stream can be decoded, as is, by any standard compliant decoder.
The UHT-JPEG-E core is designed with simple, fully controllable and FIFO-like, streaming input and output interfaces. Being carefully designed and rigorously verified, the UHT-JPEG-E is a reliable and easy-to-use and integrate IP.
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