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UHT-JPEG-D, Ultra High Throughput JPEG Decoder-ip-21844
￥10,000.00
| 供应商 | ALMA Technologies |
|---|---|
| 型号 | Up to 32 decoded samples per clock cycle of 8/10/12-bit per component image or video data |
| 类型 | Soft IP |
| 到期日 | Silicon proven |
| 源网址 | View more |
| 特征 | Ultra high throughput in low-end silicon 4:4:4, 4:2:2, 4:2:0 and 4:0:0 (grayscale) image or video data decoding 8-, 10- and 12-bit per component sample depth Up to 32 samples per clock cycle decoding, using scalable and transparent parallel processing Single JPEG byte stream input and single - multiple pixels - raster scan interleaved output Algorithmic decoding latency of approximately 32 scan lines for 4:2:0 and 16 scan lines for all other sampling formats Configurable full on-chip or mixed on/off-chip memories implementation CPU-less, complete and standalone operation |
| 详情页 | View more |
| 附件链接 | View more |
The UHT-JPEG-D core from Alma Technologies is a very high performance 8-bit Baseline and 12-bit Extended JPEG decoder, designed to enable the massive pixel rates of 4K/8K resolutions and high frame rate video applications in highly cost-effective FPGA and ASIC implementations.
The UHT-JPEG-D accepts the standalone and standard compliant JPEG byte stream generated by the Alma Technologies UHT-JPEG-E encoder, or other compatible JPEG byte stream, and outputs the decoded data in interleaved raster scan format. It supports decoding of 4:4:4, 4:2:2, 4:2:0 and 4:0:0 (grayscale) image or video streams, in 8-, 10- or 12-bit per component sample depths. The UHT-JPEG-D can be implemented using only on-chip memory resources, while using off-chip memory too is also natively supported. Designed with a user configurable architecture, the decoder scales to offer a sustained decoding throughput from 1 to 32 samples per clock cycle.
Using multiple internal processing engines, the UHT-JPEG-D core offers the needed performance through its scalable parallel architecture. The input JPEG stream is split internally into chunks and each chunk is assigned to one of multiple internal decoding units. This is done in a way which is totally transparent to the system utilizing the IP, abstracting all the parallelization complexity from the rest SoC components. The number of internal decoding units is configurable before synthesis, adapting to the implementation technology speed, and non-critical resources are shared between the multiple engines.
The UHT-JPEG-D uses a single compressed data input interface and produces raster scan interleaved decoded image or video data through a single - multiple pixels - output interface. Its operation is completely standalone, without needing any host CPU or GPU power.
The UHT-JPEG-D core is designed with simple, fully controllable and FIFO-like, streaming input and output interfaces. Being carefully designed and rigorously verified, the UHT-JPEG-D is a reliable and easy-to-use and integrate IP.
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