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| 供应商 | Arasan Chip Systems |
|---|---|
| 型号 | UFS Host Controller IP |
| 类型 | Soft IP |
| 到期日 | Silicon proven |
| 源网址 | View more |
| 特征 | Definable write-protect group size Boot mode operation Device enumeration and discovery Background operations Secure Erase and Trim operations enhance security Write-protect options include permanent and power-on protection Proven UniPro link layer High-performance MIPI M-PHY Unencrypted source code for easy implementation |
| 详情页 | View more |
| 附件链接 | View more |
The Universal Flash Storage (UFS) is a MIPI data transfer standard is designed for mobile systems.
Most UFS applications require large storage capacity for data and boot code. Applications include mobile phones, UMPC, DSC, PMP, MP3 and other applications requiring mass storage, boot storage, XiP or external cards. The UFS standard is a simple, but high-performance, serial interface that efficiently moves data between a host processor and mass storage devices.
UFS transfers follow the SCSI model, but with a superset of SCSI commands. The Arasan UFS Host controller uses an M-PHY backed by a UniPro Link layer controller as per the specification. There is a Host controller state machine and a FIFO to buffer data in each direction. The processor accesses the Host registers and DMA engine over the AHB or other interface. Transfers are initiated by the UFS driver which also writes the UFS Host Controller Interface (UFSHCI) registers to manage Host operation. The Arasan UFS IP core is an RTL design in Verilog that implements a Host on an ASIC, or FPGA. The core includes RTL code, test scripts and a test environment for full simulation verifications. The Arasan UFS IP core has been widely used in different applications by major device vendors.
Most UFS applications require large storage capacity for data and boot code. Applications include mobile phones, UMPC, DSC, PMP, MP3 and other applications requiring mass storage, boot storage, XiP or external cards. The UFS standard is a simple, but high-performance, serial interface that efficiently moves data between a host processor and mass storage devices.
UFS transfers follow the SCSI model, but with a superset of SCSI commands. The Arasan UFS Host controller uses an M-PHY backed by a UniPro Link layer controller as per the specification. There is a Host controller state machine and a FIFO to buffer data in each direction. The processor accesses the Host registers and DMA engine over the AHB or other interface. Transfers are initiated by the UFS driver which also writes the UFS Host Controller Interface (UFSHCI) registers to manage Host operation. The Arasan UFS IP core is an RTL design in Verilog that implements a Host on an ASIC, or FPGA. The core includes RTL code, test scripts and a test environment for full simulation verifications. The Arasan UFS IP core has been widely used in different applications by major device vendors.
FAQ - Frequently Asked Questions
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