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| 供应商 | CAST |
|---|---|
| 型号 | 40G UDP/IP Hardware Protocol Stack |
| 类型 | Soft IP |
| 到期日 | Available on request |
| 源网址 | View more |
| 特征 | Complete UDP/IP Hardware Stack supporting IPv4 without packet fragmentation, Jumbo and Super Jumbo Frames, ARP with Cache, ICMP (Ping), IGMP v3 (Multicast), UDP/IP Unicast and Multicast, DHCP (optional), VLAN (802.1Q) Standalone operation requires no software assistance. Run time programmable network parameters: Local, Destination and Gateway IP address, Source and Destination UDP ports, MAC address Ethernet Framing processing for non-UDP packets. 1 to 32 UDP transmit. and 1 to 32 UDP receive channels 512-bit data-path and AXI-Stream or Avalon-ST data interfaces |
| 详情页 | View more |
| 附件链接 | View more |
Implements a UDP/IP hardware protocol stack that enables high-speed communication over a LAN or a point-to-point connection. Designed for standalone operation, the core is ideal for offloading the host processor from the demanding task of UDP/IP encapsulation and enables media streaming with speeds up to 100Gbps even in processor-less SoC designs.
Trouble-free network operation is ensured through run-time programmability of all the required network parameters (local, destination and gateway IP addresses; UDP ports; and MAC address, etc). The core implements the Address Resolution Protocol (ARP), which is critical for multiple access networks, and the Echo Request and Reply Messages (“ping”) of the Internet Control Message Protocol (ICMP) widely used to test network connectivity. It can use a static IP address or automatically request and acquire an IP address from a Dynamic Host Configuration Server (DHCP) server. Furthermore, the core supports 801.1Q tagging and is suitable for operation in a Virtual LAN.
The core is easy to integrate into systems with or without a host processor. Packet data can be read/written to the core via dedicated AMBA? AXI4-stream or Avalon?-ST interfaces, while registers are accessible via an AXI4-Lite, or AHB or Avalon-MM slave interface. Bridges to other interface protocols can be made available upon request. The core is Ethernet MAC-independent but can be made available pre-integrated with an Altera, Xilinx, or other third-party eMAC core.
Trouble-free network operation is ensured through run-time programmability of all the required network parameters (local, destination and gateway IP addresses; UDP ports; and MAC address, etc). The core implements the Address Resolution Protocol (ARP), which is critical for multiple access networks, and the Echo Request and Reply Messages (“ping”) of the Internet Control Message Protocol (ICMP) widely used to test network connectivity. It can use a static IP address or automatically request and acquire an IP address from a Dynamic Host Configuration Server (DHCP) server. Furthermore, the core supports 801.1Q tagging and is suitable for operation in a Virtual LAN.
The core is easy to integrate into systems with or without a host processor. Packet data can be read/written to the core via dedicated AMBA? AXI4-stream or Avalon?-ST interfaces, while registers are accessible via an AXI4-Lite, or AHB or Avalon-MM slave interface. Bridges to other interface protocols can be made available upon request. The core is Ethernet MAC-independent but can be made available pre-integrated with an Altera, Xilinx, or other third-party eMAC core.
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