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| 供应商 | CAST |
|---|---|
| 型号 | TSN Ethernet Endpoint Core |
| 类型 | Soft IP |
| 到期日 | Silicon proven |
| 源网址 | View more |
| 特征 | TSN Endpoint subsystem integrating low-latency MAC, traffic scheduler, and time synchronization stack. Supports: IEEE 802.1Qav, Qbv, Qbu, Qbr, & IEEE 802.1AS Enables high-precision, sub-microsecond timing synchronization. Supports flexible bandwidth reservation and allocation per traffic class, which is essential for deterministic, low-latency, low-jitter communication AX4-Lite host interfaces, and AXI4-Stream for packet data Complete reference designs available for Intel and Xilinx FPGAs, including sample application software Proven in TSN plugfests by IIC and LNI 4.0 |
| 详情页 | View more |
| 附件链接 | View more |
The TSN-EP implements a configurable controller meant to ease the implementation of endpoints for networks complying to the Time Sensitive Networking (TSN) standards. It integrates hardware stacks for timing synchronization (IEEE 802.1AS) and traffic shaping (IEEE 802.1Qav and 802.1Qbv), and a low-latency Ethernet MAC.
The controller core is designed to enable high-precision timing synchronization and flexible yet accurate traffic scheduling. Requiring minimal software assistance for its initialization, it features extremely low and deterministic ingress and egress latencies, and simplifies the development of time-aware applications. The TSN-EP provides the system with timing information (time-stamps, alarms, etc.) that is typically required for the operation of a TSN network endpoint device. Furthermore, it allows the system to define and tune in real time the traffic shaping parameters according to an application's requirements.
The TSN-EP uses standard AMBA? interfaces to ease integration. Its configuration and status registers are accessible via a 32-bit-wide APB bus, and packet data are input and output via 32-bit-wide AXI-Streaming buses.
The TSN-EP is designed with industry best practices, and is available in synthesizable RTL (Verilog 2001) source code or as a targeted FPGA netlist. Deliverables provide everything required for a successful implementation, including sample scripts, an extensive testbench, and comprehensive documentation.
The controller core is designed to enable high-precision timing synchronization and flexible yet accurate traffic scheduling. Requiring minimal software assistance for its initialization, it features extremely low and deterministic ingress and egress latencies, and simplifies the development of time-aware applications. The TSN-EP provides the system with timing information (time-stamps, alarms, etc.) that is typically required for the operation of a TSN network endpoint device. Furthermore, it allows the system to define and tune in real time the traffic shaping parameters according to an application's requirements.
The TSN-EP uses standard AMBA? interfaces to ease integration. Its configuration and status registers are accessible via a 32-bit-wide APB bus, and packet data are input and output via 32-bit-wide AXI-Streaming buses.
The TSN-EP is designed with industry best practices, and is available in synthesizable RTL (Verilog 2001) source code or as a targeted FPGA netlist. Deliverables provide everything required for a successful implementation, including sample scripts, an extensive testbench, and comprehensive documentation.
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