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| 供应商 | CAST |
|---|---|
| 型号 | Master/Slave Octal SPI Controller |
| 类型 | Soft IP |
| 到期日 | In Production |
| 源网址 | View more |
| 特征 | Fully synchronous, scan-ready, design architecture Full duplex operation Software programmable Master or Slave mode, and SCLK rate 8-bit, 16-bit, 24-bit, and 32-bit synchronous serial transmission 16 word/byte Transmit FIFO (configuration option) 16 word/byte Receive FIFO (configuration option) Up to four slaves under Master control Interrupt control; LSB or MSB mode Tristate Slave MISO signaling for multiple slaves Technology independent HDL source code (soft core) |
| 详情页 | View more |
| 附件链接 | View more |
Implements a controller for a single-, dual-, quad-, or octal-lane Serial Peripheral Interface (SPI) bus, which can operate either as a master or as a slave.
Designed to work with a wide variety of SPI-bus variants, the core supports run-time control of several SPI protocol parameters. For example, the SPI frame width can be 1 to 4 bytes, the most-significant bit position in a frame, serial clock phase and polarity are all software-programmable. In master mode the core can control up to 32 slaves. A software-controllable clock generator derives the serial clock for master mode, by dividing the frequency of a clock line dedicated for that purpose.
The SPI-MS provides access to is status and control registers, and to the SPI transfer data via a 32-bit APB slave interface. The core treats the APB and SPI clocks as asynchronous to each other, and implements a clean clock-domain crossing boundary. The core implements two configurable-depth FIFOs, one for the receiver and one for the transmitter path. To ease integration, an interrupt can be generated to indicate availability of a programmable amount of received data or availability to transmit a programmable amount of new data.
The SPI-MS core is rigorously verified, silicon-proven and available in RTL source or as a targeted FPGA netlist.
Designed to work with a wide variety of SPI-bus variants, the core supports run-time control of several SPI protocol parameters. For example, the SPI frame width can be 1 to 4 bytes, the most-significant bit position in a frame, serial clock phase and polarity are all software-programmable. In master mode the core can control up to 32 slaves. A software-controllable clock generator derives the serial clock for master mode, by dividing the frequency of a clock line dedicated for that purpose.
The SPI-MS provides access to is status and control registers, and to the SPI transfer data via a 32-bit APB slave interface. The core treats the APB and SPI clocks as asynchronous to each other, and implements a clean clock-domain crossing boundary. The core implements two configurable-depth FIFOs, one for the receiver and one for the transmitter path. To ease integration, an interrupt can be generated to indicate availability of a programmable amount of received data or availability to transmit a programmable amount of new data.
The SPI-MS core is rigorously verified, silicon-proven and available in RTL source or as a targeted FPGA netlist.
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