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SPI-MEM-CTRL, Quad SPI-Flash Controller-ip-21191
￥10,000.00
| 供应商 | ALMA Technologies |
|---|---|
| 型号 | Quad SPI Flash Memory Controller |
| 类型 | Soft IP |
| 到期日 | Silicon proven |
| 源网址 | View more |
| 特征 | Automatic identification of a variety of memories Configurable memory features to allow support for more serial flash devices Efficient Bandwidth Utilization Flexible Access Model Supports a requests based block read interface Can be configured to read memory contents after power-on, without any programming Features an additional cached random access interface for direct execution of code |
| 详情页 | View more |
| 附件链接 | View more |
The Alma Technologies SPI-MEM-CTRL IP core offers the interconnection between a host and a serial flash memory using the Serial Peripheral Interface. The SPI-MEM-CTRL supports Single, Dual Input, Dual Input/Output and Quad Input/Output SPI accesses.
The core automatically identifies a variety of serial flash memories and communicates with the attached device at the maximum possible bandwidth. Register accesses are used to insert access requests and read/write data into/out SPI-MEM-CTRL core. Communication with devices other than those automatically identified, is also feasible as the core can be programmed with the memory device parameters. The SPI-MEM-CTRL can read, write or erase any part of the memory.
The core is rigorously verified. A complete verification environment that helps designers verify the functionality and compliance of the core, and additional aids for system-level simulation are available.
The core automatically identifies a variety of serial flash memories and communicates with the attached device at the maximum possible bandwidth. Register accesses are used to insert access requests and read/write data into/out SPI-MEM-CTRL core. Communication with devices other than those automatically identified, is also feasible as the core can be programmed with the memory device parameters. The SPI-MEM-CTRL can read, write or erase any part of the memory.
The core is rigorously verified. A complete verification environment that helps designers verify the functionality and compliance of the core, and additional aids for system-level simulation are available.
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