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供应商	VeriSilicon
型号	SMIC 0.18um 1.8v APLL
类型	Hard IP
到期日	Pre-silicon
源网址	View more
特征	Process: SMIC 0.18um 1P6M CMOS logic process Supply voltage: 1.8v±10% Input reference clock frequency range: 30KHZ ~ 3MHZ Output clock CLK1 frequency range: 70MHZ ~ 150MHZ On chip filter capacitances Current: <3mA Operating junction temperature: - 40?'￠????"?°C ~ +25?'￠????"?°C ~ +125?'￠????"?°C Two output clocks: - CLKP: standard output from the output divider;- CLK1: output from VCO directly
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详情

This IP is a programmable Analog PLL suitable for low frequency reference clock and large feedback clock divider. It contains a 1-32 input clock divider, a 1024-4578 feedback clock divider and a 1-8 output clock divider. By setting DM[4:0], DN[12:0] and DP[2:0] to different values according to different REFIN, CLK1 and CLKP will be locked at the multiples of input frequency.

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