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| 供应商 | T2M |
|---|---|
| 型号 | ISO 7816 based Smart Card Reader IP |
| 类型 | Soft IP |
| 到期日 | In Production |
| 源网址 | View more |
| 特征 | Compatible with the ISO 7816-3: 2006 and EMV 4.2/4.3 standard Support for asynchronous Smart Cards Dual configurable length FIFO with two programmable thresholds Card detection input Software-configurable interrupts Automatic convention detection and decoding Programmable non-gated card clock generator Automatic ETU generator DMA support for transmit and receive Hardware CRC and LRC calculations |
| 详情页 | View more |
| 附件链接 | View more |
The DSMART is a fast, versatile and cost-competitive core intended for smart card reader applications. It provides a communication interface with a smart card based on ISO 7816-3/EMV4.2/4.3 requirements. The DSMART IP Core implements hardware support for both T0 character oriented protocol and T1 block oriented protocol. It was designed to combine highly reduced CPU utilization and low area consumption. The DSMART is able to activate and deactivate cards, perform resets, handle ATR reception and offers many additional features. Configuration options allow you to adjust the DSMART to your particular needs and choose proprietary options, which will be the most suitable for the design. Data transfer to and from the host system can be interrupt-driven or executed through Direct Memory Access (DMA). The automatic convention detection and decoding mechanism ensure the exact result regardless of the used convention. Elementary Time Unit (ETU) ￠??" time duration of one bit is decoded from the received ATR interface byte and generated automatically. The card clock divider provides non-gated clock with a wide range of possible frequencies. A special power down mode was implemented in which the card clock is being held in two possible states, depending on the card parameter. An error signaling and character repetition are automatic for the T0 protocol. The DSMART also incorporates optional CRC/LRC hardware checking and generation mechanism, which gives a convention-independent result. The received CRC/LRC is not stored in the FIFO but can be read in case of CRC/LRC error. Additionally the optional block length counter provides security of the DMA block transfer and automatic CRC/LRC, subjoining with a manual affixing option. A special block mode handles block transfer automatically. Status and error registers provide necessary information about the FIFO state, errors and card events.
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