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SD 4.0 / SDIO 4.0 / eMMC 5.0 Host Controller-ip-21246
￥10,000.00
| 供应商 | Arasan Chip Systems |
|---|---|
| 型号 | SD 4.0 / SDIO 4.0 / eMMC 5.0 Host Controller IP |
| 类型 | Soft IP |
| 到期日 | Silicon proven |
| 源网址 | View more |
| 特征 | Supports AHB, AXI or OCP System/Host Interfaces Supports 32-bit and 64-bit system bus Compliant with SDIO specification Version 4.00 Compliant with SD Host controller Version 4.00 Compliant with eMMC Specification Version 5.0 Supports UHS-II data transfer rates between 390Mb/s to 1.56Gb/s eMMC HS400 supports 400 MB/s data rate Supports eMMC5.0 Security Protocol Commands Supports 32-bit and 64-bit system bus eMMC Backward compatible to 1-bit, 4-bit and 8-bit modes Silicon proven in TSMC 28nmHPM |
| 详情页 | View more |
| 附件链接 | View more |
The SD 4.0/SDIO 4.0/eMMC 5.0 Host Controller IP from Arasan Chip Systems is a highly integrated host controller IP solution that supports three key memory card I/O technologies:
- SD4.0
- SDIO4.0
- eMMC5.0
This IP handles all of the timing and interface protocol requirements to access these media as well as processing the commands in hardware thereby scaling in both performance and access speeds. The IP supports connection to a single slot and performs multi-block writes and erases that lower access overhead. In addition, a host can utilize this IP to boot directly from an attached eMMC memory, thereby simplifying system initialization during power up. The SD4 / eMMC5.0 host interface is based on a standard 32-bit AXI bus which is used to transfer data and configure the IP.
Benefits
Fully compliant, silicon-proven core
Premier direct support from Arasan IP core designers
Easy-to-use industry standard test environment
Unencrypted source code allows easy implementation
Reuse Methodology Manual guidelines (RMM) compliant verilog code ensured using Spyglass
- SD4.0
- SDIO4.0
- eMMC5.0
This IP handles all of the timing and interface protocol requirements to access these media as well as processing the commands in hardware thereby scaling in both performance and access speeds. The IP supports connection to a single slot and performs multi-block writes and erases that lower access overhead. In addition, a host can utilize this IP to boot directly from an attached eMMC memory, thereby simplifying system initialization during power up. The SD4 / eMMC5.0 host interface is based on a standard 32-bit AXI bus which is used to transfer data and configure the IP.
Benefits
Fully compliant, silicon-proven core
Premier direct support from Arasan IP core designers
Easy-to-use industry standard test environment
Unencrypted source code allows easy implementation
Reuse Methodology Manual guidelines (RMM) compliant verilog code ensured using Spyglass
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