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| 供应商 | Arasan Chip Systems |
|---|---|
| 型号 | SD 4.0 Device IP Core |
| 类型 | Soft IP |
| 到期日 | In Production |
| 源网址 | View more |
| 特征 | Compliant with SD Specification 4.0 Transfers up to 312 MB/s (UHS156, 52MHz) and supports Half duplex(312 MB/s) and Full duplex (156 MB/s) in SD4.0 mode Low voltage and low power consumption with enhanced power management using new power Control mode by allowing LPS (Low power states like – EIDL and DORMANT) High-performance UHS-II PHY or UHS-I Host connection Host clock rate from 0 to 208 MHz (SDR 104) Supports SPI (Only SD3.0), 1-bit, and 4-bit SD modes Supports all SD form factors including standard, mini and micro SD card Bus Master with Scatter Gather DMA Dual operating voltage range 2.7V – 3.6V and 1.7V - 1.95V Maximum 104 MB/s read/write with 4-bit data lines in SD3.0 mode |
| 详情页 | View more |
| 附件链接 | View more |
The SD 4.0 Device IP core is used to implement SD cards connected to a Host processor over standard SD bus. The flexible architecture of SD Device IP core is targeted to develop a range of memory cards.
The SD 4.0 Device IP core is fully compliant with the SD specification. It supports the dual row pin memory cards with D0+- and D1+- pins for differential signaling . Differential clock (RCLK) can be tuned in the range of 26Mhz to 52Mhz. It also supports SPI (Only SD3.0), SD1, and SD4 bit transfer modes, and multiple functions per card. High-speed and full speed
SD data transfers are also supported to capacities up to 2TB. All version 4.0 features are supported including the UHS-II PHY, SDHS, mini-SD, and micro SD extended 2.7-3.6V operating voltages. The SD Device controller includes a bidirectional FIFO that is expandable from 4 x 32-bit to any size required.
The SD 4.0 Device supports Half duplex(312 MB/s) and Full duplex(156 MB/s) in SD4.0 mode. It also supports low voltage and low power consumption with enhanced power management using new power Control mode by allowing LPS (Low power states like – EIDL and DORMANT)
The controller integrates a Scatter Gather DMA engine automating data transfers between the SD card and system memory.
The SD Device core is available with many system bus interfaces including AHB, AXI, OCP. The wide selection of interfaces enables the core to integrate effectively SOC designs today.
The Device controller supports SD1, SD4, and SPI transfer modes. The control logic includes the 16 bit CRC generator/checker for Data and Command on SD4.0, a 7 bit CRC generator/checker (Only SD 3.0) for the command and response lines, transmitter and receiver state machines, an interrupt state machine, master state machine, command decoder, and the response generator.
The SD 4.0 Device IP core is fully compliant with the SD specification. It supports the dual row pin memory cards with D0+- and D1+- pins for differential signaling . Differential clock (RCLK) can be tuned in the range of 26Mhz to 52Mhz. It also supports SPI (Only SD3.0), SD1, and SD4 bit transfer modes, and multiple functions per card. High-speed and full speed
SD data transfers are also supported to capacities up to 2TB. All version 4.0 features are supported including the UHS-II PHY, SDHS, mini-SD, and micro SD extended 2.7-3.6V operating voltages. The SD Device controller includes a bidirectional FIFO that is expandable from 4 x 32-bit to any size required.
The SD 4.0 Device supports Half duplex(312 MB/s) and Full duplex(156 MB/s) in SD4.0 mode. It also supports low voltage and low power consumption with enhanced power management using new power Control mode by allowing LPS (Low power states like – EIDL and DORMANT)
The controller integrates a Scatter Gather DMA engine automating data transfers between the SD card and system memory.
The SD Device core is available with many system bus interfaces including AHB, AXI, OCP. The wide selection of interfaces enables the core to integrate effectively SOC designs today.
The Device controller supports SD1, SD4, and SPI transfer modes. The control logic includes the 16 bit CRC generator/checker for Data and Command on SD4.0, a 7 bit CRC generator/checker (Only SD 3.0) for the command and response lines, transmitter and receiver state machines, an interrupt state machine, master state machine, command decoder, and the response generator.
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