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| 供应商 | CAST |
|---|---|
| 型号 | Smart Card Reader Controller Core |
| 类型 | Soft IP |
| 到期日 | In Production |
| 源网址 | View more |
| 特征 | Supports the ISO/IEC 7816-3:2006 and EMV2000 4.2 specifications Performs functions needed for complete smart card sessions, including: Card activation and deactivation Cold/warm reset Answer to Reset (ATR) response reception Data transfers to and from the card Extensive interrupt support system Adjustable clock rate and bit (baud) rate Configurable automatic byte repetition Handles commonly used communication protocols: T=0 for asynchronous half-duplex character transmission, and T=1 for asynchronous half-duplex block transmission Automatic convention detection Automatic voltage class selection Adjustable FIFOs for Receive and Transmit buffers (up to 32k characters) with threshold Configurable timing functions: Smart card activation time Guard time Timeout timers Supports synchronous and any other non-ISO 7816 and non-EMV’96 or EMV2000 cards Standard system interface wrapper architecture for easy integration with host systems Fully-synchronous design suitable for scan-based testing Available in synthesizable HDL source code (versions for FPGAs also available) |
| 详情页 | View more |
| 附件链接 | View more |
Implements an interface and controller for communicating between smart cards and host systems using a variety of standard system interfaces. The SCR supports the ISO/IEC 7816-3:2006 and EMV2000 4.2 specifications, which define the electrical signals and transmission protocols for smart cards (also known as integrated circuit cards). It acts as a communication controller, passing data to and from the host system and the smart card. It is fully-featured, and can activate and deactivate cards, perform cold/warm resets, handle ATR response reception, and execute other essential functions. The SCR consists of the core smart card reader logic with a wrapper for the desired system interface. (AMBA APB and Wishbone interfaces are available; support for other bus interfaces is optional.) The core is fully synchronous for easier testing and is designed for efficient ASIC or FPGA implementation. It requires, for example, just 6,500 ASIC gates and operates at 300 MHz (TSMC 0.13). This core can be mapped to any any Intel, Lattice, MicroSemi, or Xilinx programmable device, or to any ASIC technology, provided sufficient silicon resources are available. Please contact CAST Sales to get accurate characterization data for your specific implementation requirements.
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