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Compliance to the AMBA Specification for easy integration into SoC implementation
Master of slave operation
Programmable clock bit rate and prescale
Separate transmit and receive first-in, firt-out memory buffers, 16bits wde, 8 locations deep
Programmable choice of interface operation, SPI, Microwire, or TI synchronous serial
Programmable data frame size from 4 to 16 bits
Independent masking of transmit FIFO, receive FIFO, and receive overrun interrupts
Internal loopback test mode available
Suport for Direct memory Access (DMA)
Identification registers that uniquely indetify the PrimeCell SSP. These can be used by an operating system to automatically configure intself
Synchronous Serial Interface (Master and Slave): Supports Motorola SPI, Ti SSI and Microwire. The PrimeCell SSP is a master or slave interface for synchronous serial communication with peripheral devices that have either Motorola SPI, National Semiconductor Microwire or Texas Instruments synchronous serial interfaces. The PrimeCell SSP performs serial-to-parallel conversion on data received from peripheral device.
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