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| 供应商 | Cadence |
|---|---|
| 型号 | Cadence 32G NRZ multi-protocol PHY |
| 类型 | Hard IP |
| 到期日 | Silicon proven |
| 源网址 | View more |
| 特征 | High-performance PHY for data center applications Low-latency, long-reach, and low-power modes Wide range of protocols that support networking, storage, and computing applications Multi-protocol support for application flexibility Non-destructive on-chip EyeSurf oscilloscope interface Extensive set of isolation, test modes, and loop-backs including APB and JTAG Supports 20-bit and 32-bit PIPE and non-PIPE interfaces Selectable serial pin polarity reversal for both transmit and receive paths |
| 详情页 | View more |
| 附件链接 | View more |
The Cadence? 32/25Gbps Multi-Link and Multi-Protocol PHY IP for TSMC 7nm FinFET is a high-performance SerDes operating from 1.25Gbps to 32Gbps and specifically designed for infrastructure and data center applications. It features long-reach equalization capability at very low active and standby power. The SerDes offers very low latency for timecritical applications for enterprise-level data communications, networking, and storage systems. The PHY IP provides extensive flexibility to mix and match protocols within the same macro. The PHY IP is designed to run PCI Express? (PCIe?), Compute Express Link (CXL), 25GKR, and 10G-KR. Multiple test features are embedded and easily accessible by the end user. A user-friendly graphical interface called EyeSurf provides convenient access to real-time and non- destructive eye scope and bathtubs for monitoring the bit error rate (BER) and the link performance during live traffic. The PHY IP quickly and easily integrates into any system on chip (SoC) and connects seamlessly to the Cadence controller for full flexibility. This minimizes time and risk of device development. It offers integrators the advanced capabilities, flexibilities, and support for advanced, high-performance designs.
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