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PCIe Multifunction IP for Intel Cyclone 5 / Arria 5 FPGAs-ip-22719
￥10,000.00
| 供应商 | Smartlogic GmbH |
|---|---|
| 型号 | The PCI Express specification allows endpoints that incorporate more than one physical PCIe function. |
| 类型 | Soft IP |
| 到期日 | In Production |
| 源网址 | View more |
| 特征 | Utilizes the Intel PCIe HIP block with up to 8 physical PCIe functions. Designs provides up to 8 AXI masters which can be freely mapped to the PCIe functions Optional DMA support (Flex or HCC IP core) The user defines, if all PCIe functions communicate with either the same or with a different device driver 32 and 64-Bit BAR support for all functions BARs can be defined independently at compile time. Each function can issue interrupts (MSI Interrupts recommended) Device driver package available as option Link speeds Gen 1 or 2, Link width x1-x4, (x8 possible with Arria V) Available for Cyclone V and Arria V FPGAs (ask for the availability for other FPGA families) |
| 详情页 | View more |
| 附件链接 | View more |
The PCI Express specification allows endpoints
that incorporate more than one physical PCIe
function. Such endpoints are called
multifunction devices. The big advantage of a
multifunction device is, that a separate device
driver can be associated to each physical
function. This simplifies driver development and
maintenance significantly by separating the
peripheral functions logically into different
device drivers.
The Intel PCIe hardblocks in the Cyclone V /
Arria V FPGA device families support multi function devices natively but on a very low
level.
Smartlogics PCI Express multifunction IP core
for Cyclone V FPGAs offers a fully productized
IP core with optional DMA support. The core
operates with industry standard interfaces (AXI
and AXI Stream) and encapsulates the whole
PCI Express protocol know-how. This frees the
FPGA designer to concentrate on the project
specific design tasks.
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