PCIe 5.0 SerDes PHY-ip-17792

¥10,000.00
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SKU
ip-17792
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供应商 Rambus
型号 The Rambus PCI Express (PCIe) 5.0 and Compute Express Link (CXL) PHY is a low-power, area-optimized, silicon IP core designed wi
类型 Hard IP
到期日 In Production
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特征 Complete SerDes subsystem solution with co-validated Expresso 5.0 digital controller core from Northwest Logic, a Rambus company PIPE 5.2-compliant interface for integration with 3rd-party controllers PHY supports CXL interface specification Duplex lane configurations of x1, x2, x4, x8 and x16 with bifurcation support Flexible ASIC clocking Multi-tap Tx Finite Impulse Response (FIR) equalizer with multi-level de-emphasis Continuous-time linear equalizer (CTLE) and multi-tap decision feedback equalizer (DFE) capable of compensating more than 36dB of channel insertion loss across PVT Support for transmitter and receiver spread spectrum clocking (SSC) to meet FCC regulations for electro-magnetic interference (EMI) Expandable register interface enabling communication with multiple PMAs and PCS-BIST soft macros Built-in self test (BIST) with ATPG and AC/DC Boundary scan support
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The Rambus PCI Express (PCIe) 5.0 and Compute Express Link (CXL) PHY is a low-power, area-optimized, silicon IP core designed with a system-oriented approach to maximize flexibility and ease of integration. It delivers up to 32 GT/s data rates in performance-intensive applications for artificial intelligence (AI), data center, edge, 5G infrastructure and graphics. With the Rambus PCIe 5.0 controller core it comprises a complete PCIe 5.0 SerDes subsystem. Alternatively, it can be integrated with PIPE 5.2-compliant 3rd-party controllers. The PCIe 5 SerDes PHY supports PCIe 5.0, 4.0, 3.0 and 2.0, and has full support for manufacturability. How PCIe 5.0 Works The Rambus PCIe 5.0 PHY with the Rambus PCIe 5.0 digital controller comprise a high-performance serial link subsystem. Optimized for power in challenging, high-loss channels, our PCIe 5.0 interface solution is ideal for performance-intensive AI, data center, edge, 5G infrastructure and graphics applications. The PHY consists of a PMA hard macro that supports PCIe 5.0, 4.0, 3.0 and 2.0 protocols and a physical coding sublayer (PCS) soft macro for PCIe that is PIPE 5.2 compliant. Co-verified with the PCIe 5.0 digital controller, the PHY can also be integrated with 3rd-party PIPE 5.2-compliant controllers.

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