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| 供应商 | T2M |
|---|---|
| 型号 | PCIe 2.0 Serdes PHY IP, Silicon Proven in TSMC 22ULP/ULL |
| 类型 | Soft IP |
| 到期日 | Silicon proven |
| 源网址 | View more |
| 特征 | Compatible with PCIe base Specification Full compatible with PIPE4.2 interface specification Independent channel power down control Implemented Receiver equalization Adaptive-CTLE to compensate insertion loss Support 16-bit/32bit parallel interface Support for PCIe gen1(2.5Gbps) and PCIe gen2(5.0Gbps) Support flexible reference clock frequency Support 100MHz differential reference clock input or output (with SSC optionally) in PCIe Mode Support Spread-Spectrum clock (SSC) generation and receiving from -5000ppm to 0ppm Support programmable transmit amplitude and Deemphasis |
| 详情页 | View more |
| 附件链接 | View more |
The PCIe2.0 PHY IP is an all-in-one physical layer (PHY) IP solution for mobile and consumer applications. The PHY IP includes mixed-signal circuits to handle both 2.5GT/s and 5.0GT/s data transfer speeds while adhering to the PCIe2.0 basic standards. The PCIe2.0 PHY IP is made up of two layers: the Physical Media Attachment (PMA) layer and the Physical Coding Sublayer (PCS), and it simply links to either the PCIe2.0 MAC layer via the standard PIPE-3.0 interface.
The PCIe2.0 PHY IP transceiver is optimized for low power consumption and minimal die area, without sacrificing performance and high-data throughput. The PCIe2.0 PHY IP comprises a complete on-chip physical transceiver solution with Electrostatic Discharge (ESD) protection, built-in self-test module with embedded jitter injection, and a dynamic equalization circuit that ensures full support for high performance designs
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