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供应商 | T2M |
---|---|
型号 | PCI Gen4.0 16Gbps PHY IP |
类型 | Hard IP |
到期日 | Silicon proven |
源网址 | View more |
特征 | Compliments to PCI Express base specification 4.0 and backward compatibility QUAD PCI Express 16/8/5/2.5Gbps per LANE and available in QUAD configuration Lowest latency in the Industry and Adaptive CTLE and 3 tap DEF receive equalization Configurable parallel data width of 8,16,32 Single Supply voltage of 0.9V, Temp -40 to 125 deg C Tight control over termination resistor ( ~ 50 ohm) with on chip calibration Input reference clock of 100MHz to support 2.5G/5G/8G/16G data rates Support AC/DC coupled modes, Programmable VGA and Peak amp to support different cable applications Separate Amplitude path for Eye-diagram monitoring/DFE tap calibration/offset calibration CDR logic for better data alignment and locking , 3 taps TX equalization ( pre, main, post cursor ) , Programmable pre-emphasis |
详情页 | View more |
附件链接 | View more |
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