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| 供应商 | Cadence |
|---|---|
| 型号 | Application-optimized, high-performance controller IP for PCIe |
| 类型 | Soft IP |
| 到期日 | Silicon proven |
| 源网址 | View more |
| 特征 | Compliant with PCIe 3.1, 2.1, and 1.1 specifications Configurable as Root Complex, Endpoint, or Dual Mode Ultra-low transmit/receive latency and high bandwidth Supports x1, x2, x4, x8, and x16 configurations Single-Root I/O Virtua Up to 256 PCI Physical Functions or Virtual Functions with Alternative Requester ID Interpretation support AMBA 3/4 AXI and HAL client interface options 16- or 32-bit PIPE 4.2 interface Available separate PCLK input for PIPE interface Optional enhanced power management control |
| 详情页 | View more |
| 附件链接 | View more |
The Cadence? Controller IP for PCIe? 3.1 is a solution created for mobile applications that provides the means for these goals. It has the logic required to integrate a Root Complex (RC), Endpoint (EP), or Dual Mode (DM) controller into any system on chip (SoC). Compliant with PCI Express? 3.1, 2.1, and 1.1 specifications, the Controller IP has over then 100 configuration features, and 1500+ input parameters, to customize the controller to the specific needs of any application. The Controller IP is architected to quickly and easily integrate into any SoC, and connect seamlessly to a Cadence or third-party PIPE 4.2-compliant PHY. Client applications access the controller through the industry-standard Arm? AMBA? 3 or 4 AXI interface or through Cadence's native Host Adaptation Layer (HAL) interface.
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