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供应商	Alphawave Semi
型号	OpenFive HBM2/2E (High Bandwidth Memory) Subsystem IP
类型	Hard IP
到期日	Silicon proven
源网址	View more
特征	HBM Controller: JEDEC DRAM Specification compliant Supports up to 3.2 Gbps per pin data rate Configurable Independent HBM Channel support Low latency operation HBM PHY: Ultra-low latency Coarse and Fine grain IO training Low power HBM memory and PHY modes Loopback support for Testability CMOS IO with programmable drive strengths Lane Repair features
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OpenFive's HBM IP is the industry's first comprehensive solution for integrating high-bandwidth memory into ASICs thereby achieving the ultimate high performance and low power. By integrating the HBM protocol controller, PHY and IO into one sub-system IP product, interoperability aspects between the different system components are addressed. As an early advocate of 2.5D and 3D ASIC design technologies and by leveraging its experience from the industry's first successful 2.5D SoC SiP demonstration in 2013, OpenFive plays a key role in enabling industry applications to leverage the HBM 3D-stacked DRAM technology.

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