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供应商	Alphawave Semi
型号	D2D PHY IP (Die-to-Die Interface)
类型	Hard IP
到期日	Silicon proven
源网址	View more
特征	D2D PHY signals are single ended (Single Duplex) and are based on HBM Memory Electrical IOs Each channel is made up of 42 pairs of Tx/Rx signals that runs at configurable 4Gbps/8Gbps/16Gbps contributing up to ~1.75Tbps/mm Channel lengths support up to 5mm with latency less than 5ns (Other combinations are available) Best in the industry less than 0.5 pJ/bit power consumption Built-in PLL to support differential clock forwarding Self-contained initialization and calibration state machines No requirement of Forward Error Correction (FEC) IP as signal supports best in the industry channel BER up to 1E-21 Programmable output drivers Compatible to various parallel wire specification in the industry
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附件链接	View more

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Die-to-Die (D2D) PHY IP is based on HBM electrical specification and will also be compatible with upcoming interface standards. It is used specifically for heterogenous chiplet solutions in wired communications, AI, and HPC applications. With recent advances in package technologies, it is possible to route high-speed signals within a package connecting multiple die either on Interposer or on Organic Substrate. Die-to-Die PHY IP offers a unique value proposition in terms of low power, high throughput, and low latency links enabling faster time to integration.

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