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| 供应商 | Noesis Technologies |
|---|---|
| 型号 | ITU G.704 T1 Framer/Deframer |
| 类型 | Soft IP |
| 到期日 | Silicon proven |
| 源网址 | View more |
| 特征 | T1 Framer/Deframer compliant to G.704, G.706, G.732 and O.163 ITU recommendations Supports superframe and extended superframe framing standards Supports CRC6 / non-CRC6 cases Three zero suppression modes (B7 stuffing, B8ZS, Transparent) User configurable receive and transmit control Supports microprocessor or hardware control mode Supports loop-back mode, alarm generation, alarm detection and error logging Compatible with Dallas DS2186 transmit line interface Fully synchronous design Silicon proven in ASIC and FPGA technologies for a variety of applications |
| 详情页 | View more |
| 附件名称 | ntT1_G704_pb.pdf |
| 附件链接 | View more |
Noesis Technologies ntT1_G704 Framer/Deframer is designed for T1 networks and is compliant with ITU recommendations G.704, G.706, G.732, G.775 and O.163. The core provides all the necessary data formatting transforms for transmission over an T1 carrier. T1 is one of the two most widely used TDM (time division multiplexing) carriers incorporating 24 channels, each with a bandwidth of 64 kbps providing a total payload bit rate of 1536 kbps.
The ntT1_G704 IP core provides a flexible interface supporting hardware and microprocessor modes. Specifically the core can be connected to a host system either through an 8-bit parallel microprocessor interface (HP mode) or through a set of I/O ports (HW mode). When in HP mode, the microprocessor configures and monitors the functionality of the core through a rich set of registers. When in HW mode, the core is directly controlled and monitored through a set of dedicated ports and no microprocessor control is necessary.
At the transmit side, the framer generates framing patterns, CRC6 bits, formats outgoing and signalling data, generates alarms and clock outputs for data conditioning and decoding. At the receive side, the deframer establishes frame / multiframe synchronization, extracts data, signalling and alarm flags. It provides information like frame, multiframe alignment, calculates CRC6 and counts CRC6 errors.
The ntT1_G704 IP core provides a flexible interface supporting hardware and microprocessor modes. Specifically the core can be connected to a host system either through an 8-bit parallel microprocessor interface (HP mode) or through a set of I/O ports (HW mode). When in HP mode, the microprocessor configures and monitors the functionality of the core through a rich set of registers. When in HW mode, the core is directly controlled and monitored through a set of dedicated ports and no microprocessor control is necessary.
At the transmit side, the framer generates framing patterns, CRC6 bits, formats outgoing and signalling data, generates alarms and clock outputs for data conditioning and decoding. At the receive side, the deframer establishes frame / multiframe synchronization, extracts data, signalling and alarm flags. It provides information like frame, multiframe alignment, calculates CRC6 and counts CRC6 errors.
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