ntCH_EST-ip-19132

¥10,000.00
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SKU
ip-19132
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供应商 Noesis Technologies
型号 Programmable OFDM Channel Estimator
类型 Soft IP
到期日 Silicon proven
源网址 View more
特征 Fully configurable, high throughput, OFDM Channel Estimator. Programmable pilot patterns. Estimation based on Linear Least Squares (LS) and 1D linear interpolation algorithms for optimum trade-off between complexity and accuracy. Programmable OFDM frame size. Fully synchronous design, using single clock. Silicon proven in ASIC and FPGA technologies for a variety of applications.
详情页 View more
附件名称 ntCH_EST_pb.pdf
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The wideband OFDM signal suffers from frequency selective fading. Therefore it is necessary to identify and invert the discrete transfer function of the channel. The accurate channel estimation is achieved with the exploitation of known reference signals and pilots into the OFDM frame. The ntCH_EST core uses the pilots to determine the channel impulse response in the frequency domain. Channel estimation is performed on a block-per-block basis, where one block is composed of a programmable number of OFDM symbols. The pilot allocation and the block size is fully programmable. The ntCH_EST implements estimation formulas based on Linear Least Squares (LS) and 1D linear interpolation algorithms for optimum trade-off between complexity and accuracy. Specifically the channel estimation performs the following block based operations:
- Computation of the expected pilot positions and the expected pilot modulation.
- Isolation of the pilot subcarriers from the incoming signal.
- Averaging of the pilot values for the selected channel estimation block to achieve better estimation results.
- Applying the channel estimation formula and calculating the discrete frequency transfer function value for each pilot.
- Interpolating, using linear interpolation techniques, the estimated values in the frequency domain to extract the transfer function for the data subcarriers.
The ntCH_EST supports programmable pilot patterns and programmable OFDM frame size. It is a fully synchronous design, using single clock. It is silicon proven in ASIC and FPGA technologies for a variety of applications.

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