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| 供应商 | Mixel |
|---|---|
| 型号 | MIPI D-PHY CSI-2 TX (Transmitter) in TowerJazz 65BSB |
| 类型 | Hard IP |
| 到期日 | Available on request |
| 源网址 | View more |
| 特征 | Supports MIPI Alliance Specification for D-PHY Version 2.5 Consists of 1 Clock lane and 2 Data lanes in D-PHY mode and 80 Mbps to 1.2 Gbps data rate per lane in high-speed D-PHY mode Supports LVDS compatible with TIA/EIA-644 standard Consists of 3 channels in LVDS mode and 600 Mbit/s/channel in LVDS mode Supports both 8-bit serial data and 10-bit serial data for LVDS Embedded, high performance, and highly programmable PLL PLL has 2 independent dividers at the output of the VCO: one divider for core circuits and one for MIPI. The 2 dividers have independent settings of division factor. Supports both low-power mode and high-speed mode with integrated SERDES Supports operation with reduced amount of data lanes. Unused data lanes can be put in power-down mode in which all current paths shall be cut and no current shall flow Low power dissipation and Testability support |
| 详情页 | View more |
| 附件名称 | MXL_LVDS_DPHY_CSITX_TW_65BSB_v0.1_1pager.pdf |
| 附件链接 | View more |
The MXL-LVDS-D-PHY-CSI-TX-TW-65BSB is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specification for D-PHY v2.5 and LVDS compatible with TIA/EIA-644 standard. The PHY can be configured as a MIPI transmitter supporting camera interface CSI-2. The PHY supports mobile, IoT, virtual reality, and automotive applications.
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