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| 供应商 | Mixel |
|---|---|
| 型号 | Four Channel LVDS Receiver/Deserializer IP - Designed for Chartered 130nm |
| 类型 | Hard IP |
| 到期日 | Silicon proven |
| 源网址 | View more |
| 详情页 | View more |
| 附件名称 | MXL_LVDS_DS_4CH_180nm_3.0_1p.pdf |
| 附件链接 | View more |
The MXL-LVDS-RX-4CH is a high performance 4-channel LVDS Receiver implemented using digital CMOS technology. Both the serial and parallel data are organized into four channels. The parallel data can be 7 or 10 bits wide per channel. The input clock is 25MHz to 165MHz. The Receiver is highly integrated and requires no external components. Great care was taken to insure matching between the Data and Clock channels to maximize the receiver margin. The circuit is designed in a modular fashion and desensitized to process variations. This facilitates process migration, and results in a robust design.
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