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| 供应商 | HDL Design House |
|---|---|
| 型号 | MX25L8006E, 8 Mbit Serial Flash Memory |
| 类型 | Soft IP |
| 到期日 | Pre-silicon |
| 源网址 | View more |
| 特征 | VHDL '93, Verilog and VITAL'2000 compliant Required VITAL'2000 library for correct compilation Timing backannotation by means of an SDF files Models are written at a behavioral level, do not reveal intellectual property, and are not synthesizable |
| 详情页 | View more |
| 附件链接 | View more |
The MX25L8006E is a flash memory with standard serial interface, which supports standard 1xI/O and dual 2xI/O read, erase and program operations with power supply in 2.7V – 3.6V range. This device is Serial Peripheral Interface compatible with Mode 0 and Mode 3. Memory is organized in 16 equal 64KB blocks, or 256 equal 4KB sectors, in order to enable individual block/sector erase. The VITAL HVT MX25L behavioral model completely follows the operation capabilities of a real component. This implies complete functionality, delays between input signals and output signals and all timing requirements regarding input signals (setup and hold timings, pulse widths, etc.). Considering how important timing requirements are, this VITAL HVT MX25L behavioral model will detect and report a timing violation if constraints are not satisfied. The VITAL HVT MX25L behavioral model includes a total of 20 instructions. All instructions are implemented in this behavioral model. Also, it includes 19 timing check procedures (setup and hold, pulse width and period timing checks). This IP core has been designed and verified using Cadence state-of-the-art EDA tools, methodology and recommended design and verification flow.
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