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| 供应商 | IMEC |
|---|---|
| 型号 | This scalable specialized low power high throughput LDPC ASIP core is optimized either for IEEE802.11ad or for 11ac in 28nm CMOS |
| 类型 | Soft IP |
| 到期日 | Pre-silicon |
| 源网址 | View more |
| 特征 | Flexible power efficient ASIP processor for wireless baseband processing Instances available for IEE 802.11ad WiGig and for WLAN 802.11ac (tuned for optimal performance and energy in 28nm CMOS ; 40nm version also available) Retargetable LDPC FEC ASIP delivering world-class performance and energy The 802.11ad instance : 4 bits quantization, @500MHz throughput of 25.8 Gbps/iteration 134ns latency@3iterations, at 107000 um** [single core] (4bits) The 802.11ad instance : 35.21 mW at MCS 9 (QPSK R13/16 throughput 3.08Mbps) [core level] The 802.11ad instance: multi-cores solution for all MCS energy eff. : 3.7-4.7 pJ/bit/iteration at core level The 802.11ac instance: 5-7 bits quantization, throughput of 15.8 Gbps/iteration (R=5/6), at 383 000 um**2 The 802.11ac instance: 128.9 mW, 8.2 pJ/bit/iteration Flexible quantization scheme; assembly programmable Horizontal layered decoding, normalized/offset min-sum |
| 详情页 | View more |
| 附件链接 | View more |
Imec offers a whitebox IP license with support on a specialized LDPC (Low Density Parity Check) ASIP (Application Specific Instruction Processor) core, optimized either for IEEE 802.11ad WiGig or for WLAN 802.11ac, available both in 40nm and 28nm CMOS. Developed to meet and exceed the high throughput and low power requirements of the latest wireless standards, the FEC (Forward Error Correction) processor combines architecture and algorithm co-optimizations to get the most out of your silicon. Both 11ad and 11ac versions are tailored to support all modes in the standards at the lowest possible energy consumption. This core is assembly programmable and has flexibility at run time. The flexible quantization scheme minimizes bit widths throughout the data path. A row-based partial parallel architecture enables a trade-off between throughput and power/area efficiency: the ASIP core can be configured either as half-layer paralleled or as quarter-layer paralleled decoding. Adding modes and increasing the throughput is possible with minimal changes.
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