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供应商	M31 Technology Corporation
型号	MIPI MPHY V3.1(up to 5.8Gbps), Type-1, 1Tx1Rx, IP optimized for UFS
类型	Hard IP
到期日	Silicon proven
源网址	View more
特征	Supports RMMI interface for Type-I applications like UNIPRO protocol (UFS,CSI-3, DSI-2), LLI, SSIC and M-PCIe High speed gears, HS-G1A/B, HS-G2A/B and HS-G3A/B, with scalable power consumptions Provides hibernate or super-hibernate mode to meet mobile device requirement Burst mode CDR with short sync length ( < 16SI ) Low speed PWM Gears from G1 to G5 with ultra-low power consumptions Common lane configuration facilitates the lane scalability Low latencies to switch to/from different power states Supports multiple signal amplitudes and slew rate control for EMI reduction Supports strong BIST functions to ease the mass production tests Includes I/O pads and ESD protection cells
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附件链接	View more

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详情

MIPI M-PHY is a serial interface technology with high bandwidth capabilities, which is particularly developed for mobile applications to obtain low pin counts along with excellent power efficiency. As a MIPI Alliance contributor and leading Interface IP provider, M31 provides silicon-proven and low-power M-PHY in different process nodes. The M-PHY IP follows MIPI M-PHY v3.1 spec and supports full range of high-speed (HS) and low-speed (LS) data transfer. It is compliant to the RMMI interface which allows seamless integration with upside controllers. The M-PHY IP is optimized for UFS (Universal Flash Storage) and DigRF applications. It supports not only a very short sync length for HS transmission but also a reference-less mode during LS operation. Meanwhile, M31 also provides various lane configurations for the M-PHY IP to meet different requirements of bandwidth.

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