MIPI D-PHY / C-PHY Combo PHY for TSMC 28 nm-ip-22620

¥10,000.00
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SKU
ip-22620
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供应商 Arasan Chip Systems
型号 MIPI D-PHY / C-PHY Combo PHY for TSMC 28 nm
类型 Hard IP
到期日 Silicon proven
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特征 Compliant to MIPI Alliance Standard for C-PHY specification Version 1.2 Compliant to MIPI Alliance Standard for D-PHY specification Version 1.2 Supports asynchronous transfer at high speed mode with a symbols rate of 80-3000 MS/s on CPHY mode. Supports synchronous transfer at high speed mode with a bit rate of 80-1500 Mb/s without deskew calibration and upto 2500 Mb/s with deskew calibration on DPHY mode. Supports asynchronous transfer at low power mode with a bit rate of 10 Mb/s on both CPHY and DPHY On-chip clock generation configurable for transmitter. No external (off-chip) components required Can be ported to other processes
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附件名称 ACS_ComPhy_datasheet_v1p2.pdf
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Combination MIPI CPHY-DPHY Analog Interface - The MIPI C-PHY V1.2 improves throughput over a bandwidth limited channel, allowing more data without increased signaling clock. It is intended to be used for camera interface (CSI-2 v1.3) and display interface (DSI-2 v1.0). The signaling interface uses a 3-phase transceiver that encodes 3 bit symbols over 3 wires. This is different from the two-wire differential “lane” used in D-PHY. C-PHY was designed to coexist on the same IC pins as D-PHY so that dual-mode devices could be developed with low power signaling similar to DPHY. Arasan’s CPHY-DPHY combination provides a 3 channel C-PHY v1.2 and a four lane D-PHY v1.2 in a single IP core. This allows a seamless implementation allowing interface to D-PHY based sensors or C-PHY based sensors. Symbol encoding effectively transfers 2.286 bits per symbol compared to 1.0 bits per lane for D-PHY. The C-PHY (v1.2) operates at 3GS/s, whereas the D-PHY V1.2 (2.5Gb/s). A four lane D-PHY V1.2 provides 10Gbps which enables: 4K video at 30fps 1080p at 120fps A 3 channel C-PHY provides 17Gbps which enables: 4K video at 60fps 1080p at 240fps (for cool slow-motion videos)

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