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M25 Display Stream Compression (DSC) 1.2 Decoder-ip-21375
￥10,000.00
| 供应商 | Trilinear Technologies |
|---|---|
| 型号 | Low gate count, 8K capable, VESA DSC 1.2 compliant decoder |
| 类型 | Soft IP |
| 到期日 | In Production |
| 源网址 | View more |
| 特征 | VESA DSC 1.2 Compliant Low gate count, 350K gates Low power Implemented in FPGA for production or ASIC prototyping AMBA AXI-4 Stream Input and Output AMBA APB 4 host interface 8, 10, 12, or 16 bits per pixel 4:2:0 and 4:2:2 color spaces supported |
| 详情页 | View more |
| 附件名称 | TRI_ProductBrief_DSCDecoder_v01.pdf |
| 附件链接 | View more |
The Display Stream Compression (DSC) standard from the Video Electronics Standards Association (VESA) offers visually lossless compression for high definition (HD) video in broadcast, automotive, medical and consumer electronics applications. The Trilinear Technologies M25 DSC 1.2 Decoder offers real time decompression of HD streams with resolutions from 480p up to 8K. The decoder core is fully compliant with the VESA DSC 1.2 standard and is available for both FPGA and ASIC platforms.
The M25 core is delivered with an industry standard AMBA 3.0 Peripheral Bus interface for host configuration and decoder control. The encoded input interface is AXI4-Stream Protocol compliant and the output interface uses a streaming data structure with associated line and frame formatting signals. The DSC 1.2 Decoder core supports 8, 10, 12, 14 or 16 bits per pixel using either the RGB or YCbCr in 4:4:4 or 4:2:2 format.
The M25 DSC 1.2 Decoder core ships with a complete 'C' reference driver and a fully documented API. The core is available on the Trilinear Technologies' Cobra Development platform based on the Xilinx Kintex-7 FPGA family. This FPGA based reference system provides a complete development environment for core evaluation as well as early software development.
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