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| 供应商 | Xylon |
|---|---|
| 型号 | logiWIN captures a streaming video input which can be real-time decoded, scaled, de-interlaced, cropped and positioned. |
| 类型 | Soft IP |
| 到期日 | Silicon proven |
| 源网址 | View more |
| 特征 | IP core for Xilinx FPGA Supports ITU656 or ITU1120 (PAL, NTSC) and RGB inputs Max input and output resolutions 2048x2048 Real-time scale-up to 64x and scale-down to 16x Supports video de-interlacing, cropping, positioning Supports pixel alpha blending Embedded image color enhancements: brightness, contrast, hue, saturation Supports masked video output Configurable video memory interface: Xylon XMB, CoreConnect PLB or Xilinx MPMC Try-Before-Buy possible with no cost and no obligations |
| 详情页 | View more |
| 附件名称 | logiWIN_hds.pdf |
| 附件链接 | View more |
The logiWIN IP core accepts a streaming video input, decodes it and converts into the RGB format. The input video can be real-time scaled, de-interlaced, cropped and positioned on the video display. Captured and processed video must be displayed by a graphics controller IP, such as Xylon's logiCVC-ML Compact Multilayer Video Controller. The logiWIN integrates high-quality anti-aliasing algorithm that guarantees high picture quality without visible artifacts. The core is fully embedded into Xilinx Platform Studio and EDK tools, and its usage does not require skills beyond general Xilinx tools knowledge. Parametrizable VHDL design allows tuning of slice consumption and features set through an easy-to-use GUI interface. Instantiations of multiple logiWIN IPs enable processing of multiple video inputs within a single Xilinx FPGA device.
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