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| 供应商 | HDL Design House |
|---|---|
| 型号 | HIP 610 enables flexible and high performance data transfers in compliance with the JESD204B.01 standard release |
| 类型 | Soft IP |
| 到期日 | Silicon proven |
| 源网址 | View more |
| 特征 | Fully compatible with the JESD204B.01, 2012 standard release Uses an AMBA APB4 interface for configuration setup and status reading purposes (I2C and custom interfaces are also available upon request) Supports a wide range of data converters over single and multiple serial links Configurable number of converters per device (M), number of lanes (L) and converter resolution (N) High Density (HD) mode is available Provides initial lane alignment, frame alignment monitoring and correction, and character replacement Support for the multi-lane alignment Support for the deterministic latency (in compliance with JESD204B.01 Subclass 1 (SYSREF) and Subclass 2 deterministic latency requirements) Support for re-initialization via data interface Includes programmable debugging features and test patterns |
| 详情页 | View more |
| 附件名称 | hip_610_080.pdf |
| 附件链接 | View more |
The JESD204B RX Physical Coding Sublayer IP Core (HIP610) enables the reception of data via a configurable number of lanes from a Deserializer interface, while guaranteeing data alignment and synchronization. The HIP610 IP Core performs character boundary synchronization, 8B/10B decoding, frame recovery, lane alignment, descrambling and data demapping functions on the data stream received from the Deserializers interface. In addition, it contains a set of test features, necessary to validate the data integrity on the serial interface. The HIP610 IP Core offers the possibility to modify the behavior of the design based on the application requirements. This is done through the use of the design parameters, as well as via the Configuration Interface by programming the configuration registers. This IP core has been designed and verified using Cadence state-of-the-art EDA tools, methodology and recommended design and verification flow.
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