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供应商	Comcores
型号	JESD204B
类型	Soft IP
到期日	In Production
源网址	View more
特征	Silicon proven Widest feature set available in market Scrambling and de-scrambling included High performance Transport Layer support Build-in test functions Lint/CDC optimized UVM regression tested Interoperability tested with leading PHY/SerDes vendors
详情页	View more
附件链接	View more

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详情

The JESD204B controller IP is a highly optimized and silicon agnostic implementation of the JEDEC JESD204B.01 serial interface standard targeting both ASICs and FPGAs. The solution by default provides line-speeds of up to 12.5 Gbps per lane while guaranteeing data alignment and synchronization. The standard allows it to optionally by used up to 16 Gbps, but does not recommend running it faster due to the 8b10b encoding. The core enables quick and reliable deployment of both the transmitter (TX) and the receiver (RX) and comes optionally with a tightly integrated transport layer option, that can dynamically be configured to handle any Multiple-Converter Device Alignment, Multiple Lanes (MCDA-ML) requirements. The IP comes with the widest parameter set available and has gone through extensive testing. The IP core is silicon proven, heavily tested in UVM regression environment and has been interoperability tested with key Data Converter ADC/DAC providers and leading SerDes PHY solutions.

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