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| 供应商 | IPClock |
|---|---|
| 型号 | IPC1703 – Single chip IEEE1588v2 (PTPv2) standard compliant Master and Slave Ordinary Clock incorporate FPGA with internal CPU |
| 类型 | Soft IP |
| 到期日 | Pre-silicon |
| 源网址 | View more |
| 特征 | Single chip, Virtual Application Specific Standard Product (VASSP) provides both IEEE1588v2 Master and Slave Fully self contained IEEE 1588 product with built in processor. Remove the need for external processor Excellent wander, Fractional Frequency Offset (FFOFF) and ToD quality in packet switched networks under ITU-T G.8261 conditions Meeting UMTS, GSM/GPRS/EDGE, TD-SCDMA, WiMAX, and LTE wander, FFOFF and ToD requirements Provides best performance with low-cost oscillator Easily integrates in existing and next generation designs Standard compliant Best Master Clock (BMC) algorithm enables easy implementation of master redundancy Master locks to undisciplined 1PPS signal from GPS, 1.544MHz, 2.048MHz, 10MHz and 25MHz Upgradeable by software. Easy adding of enhancements and supporting emerging clock synchronization standards Operates with either TCXO or OCXO (10MHz, 12.8MHz, or 20MHz) |
| 详情页 | View more |
| 附件链接 | View more |
The IPC1703 utilizes IPClock's state-of-the-art technology for IEEE 1588 Slave and Master optimized for providing high quality frequency synchronization and Time of Day (ToD) over packet switched networks. Clock synchronization is required by many applications. For example, UMTS-FDD and Pseudo-wire (E1/T1) require the synchronization of frequency while LTE, WiMax, CDMA2000 and GPS replacement require frequency synchronization, phase alignment and Time of Day (ToD). The IPC1703 Virtual Application Specific Standard Product (VASSP) is a standalone "chip like" product leveraging Xilinx's Spartan-6. The IPC1703 is an application-agnostic, cost effective, reliable and standard compliant IEEE 1588 Slave and Master designed for enabling applications requiring high synchronization level. The IPC1703 is designed for easy field upgrades to support future enhancements as well as future clock synchronization standards.
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