SSTL

Stub Series Terminated Logic (SSTL) is a group of I/O standards commonly used with Double Data Rate (DDR) DRAM memory modules

SSTL_2-ip-23036
￥10,000.00
SSTL2-ip-23034
￥10,000.00
SSTL_18-ip-23028
￥10,000.00
SSTL_18-ip-23027
￥10,000.00
RGO_TSMC90_33V18_LP_30C_SSTL_18-ip-22945
￥10,000.00
RGO_TSMC40_25V18_LP_27C_SSTL_15_18-ip-22942
￥10,000.00
RGO_TSMC28_18V18_HPCP_20C_SSTL_15_18-ip-22920
￥10,000.00
2.5V DDRI/II/III SSTL/HSTL combo interface without RTT (square) - TSMC 0.13um-ip-15975
￥10,000.00
DDRI/II/III SSTL/HSTL combo interface with RTT (rectangle) - TSMC 0.13um-ip-15974
￥10,000.00
DDRI/II/III SSTL/HSTL combo interface without RTT (rectangle) - TSMC 0.13um-ip-15973
￥10,000.00
SSTL2 Interface 2.5V, 3.3V Oxide Device - TSMC 0.13um-ip-15972
￥10,000.00
DDRI/II/III SSTL/HSTL combo interface with RTT (square) - TSMC 90nm-ip-15971
￥10,000.00