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| 供应商 | Intilop |
|---|---|
| 型号 | 1G Bit TCP Offload Engine |
| 类型 | Soft IP |
| 到期日 | Silicon proven |
| 源网址 | View more |
| 特征 | Functionality Proven in multiple IDS/IPS appliances Complete header and flag processing of TCP/IP sessions in hardware à accelerates by 10x – 20x TCP Offload Engine- 2G b/s Wire-speed performance Scalable to 10 G b/s TCP + IP check sum- hardware TCP segmentation/reassembly in hardware(opt) Multiple 'slot storage' for fragmented packets Out of sequence packet detection/storage/Reassembly TCP port address tracking/automatic DMA RDMA- Data placement in Applications buffer |
| 详情页 | View more |
| 附件链接 | View more |
?Ideal for Very high performance specialized, differentiable ASICs or FPGAs for Network security or Network infrastructure applications
?Smallest logic foot print; less than 10,000 Xilinx slices, Altera ALMs or 250,000 ASIC gates + on-chip memory
?Fully integrated 1 G bit high performance Ethernet MAC.
?Scalable MAC Rx FIFOs and Tx FIFOs make it ideal for optimizing system performance.
?Hardware implementation of TCP/IP stacks' control plane and data plane.
?Hardware implementation of ARP protocol processing.
ARP table creation, deletion management (optional)
?Customizable for IP-protocol only.
?On-chip DDR or SSRAM memory controller which can address from 4K Bytes to 4 MB Bytes on chip or 256 MB off chip memories (optional)
?Simple User Side interface for easy hardware integration or a little more complicated for more power full and controlled 'Streaming' data transfers.
?Many trade-offs for some functions performed in hardware or software
?Configurable Packet buffers, session table buffers On-chip or Off-chip memories, attached DDR I/II interface. Depending on system, performance, ASIC/FPGA size requirements-> User Customizable, (optional)
?Interfaces directly to GMII, 1 G Bit Phy interfaces
?Architecture can be scaled up to 10-G bits
?Customizable to handle jumbo frames
?Integrated PCIe x 4 bus interface. x8 and x16 (opt)
?Integrated AMBA 2.0 interface or Xilinx's PLB bus for Local Processor control.
?User programmable/ prioritize-able interrupts
?Performs connection/session management
?Monitors, Stores, Maintains and processes up to 1024 live TCP sessions. Customizable to implement more, depending upon on-chip memory availability and other FPGA limitations.
?Extendable to 16K TCP sessions. Internal Memory dependent.
?Wire-speed 2-Gbps performance at full duplex
?Multiple TOEs can process up to 64K connections per second
?TCP + IP check sum generation and check performed in hardware in less than 6 clks (30 ns at 200 MHz) vs 1-2 us by typical software TCP-stack
?Connection set up and tear down/termination
?User programmable Session table parameters
?Dedicated set of hardware Timers for each TCP/IP session or customizable for sharing stale sessions.
?Multiple 'slot storage' for fragmented packets. More slots allocated when more On-chip Memory available. Self-checking available memory logic. (optional)
?Out of sequence packet detection/storage and Reassembly/Segmentation (optional)
?RDMA- Direct Data placement in Applications buffer at full wire speed without CPU-> reduces CPU's buffer copy time and utilization by 95%
?Support VLAN Bypass mode (optional)
?Easily customizable for filtering various IP and TCP traffic Protocols, directed towards any port or IP(Ideal for security appliances)
?Implements Full TCP/IP offload or By-Pass mode. (Optional)
?Future Proof- Flexible implementation of TCP Offload
?Accommodates future Specifications changes.
?Basic mini API available for easy integration with Linux/windows. Others OSs/CPUs also available.
?Smallest logic foot print; less than 10,000 Xilinx slices, Altera ALMs or 250,000 ASIC gates + on-chip memory
?Fully integrated 1 G bit high performance Ethernet MAC.
?Scalable MAC Rx FIFOs and Tx FIFOs make it ideal for optimizing system performance.
?Hardware implementation of TCP/IP stacks' control plane and data plane.
?Hardware implementation of ARP protocol processing.
ARP table creation, deletion management (optional)
?Customizable for IP-protocol only.
?On-chip DDR or SSRAM memory controller which can address from 4K Bytes to 4 MB Bytes on chip or 256 MB off chip memories (optional)
?Simple User Side interface for easy hardware integration or a little more complicated for more power full and controlled 'Streaming' data transfers.
?Many trade-offs for some functions performed in hardware or software
?Configurable Packet buffers, session table buffers On-chip or Off-chip memories, attached DDR I/II interface. Depending on system, performance, ASIC/FPGA size requirements-> User Customizable, (optional)
?Interfaces directly to GMII, 1 G Bit Phy interfaces
?Architecture can be scaled up to 10-G bits
?Customizable to handle jumbo frames
?Integrated PCIe x 4 bus interface. x8 and x16 (opt)
?Integrated AMBA 2.0 interface or Xilinx's PLB bus for Local Processor control.
?User programmable/ prioritize-able interrupts
?Performs connection/session management
?Monitors, Stores, Maintains and processes up to 1024 live TCP sessions. Customizable to implement more, depending upon on-chip memory availability and other FPGA limitations.
?Extendable to 16K TCP sessions. Internal Memory dependent.
?Wire-speed 2-Gbps performance at full duplex
?Multiple TOEs can process up to 64K connections per second
?TCP + IP check sum generation and check performed in hardware in less than 6 clks (30 ns at 200 MHz) vs 1-2 us by typical software TCP-stack
?Connection set up and tear down/termination
?User programmable Session table parameters
?Dedicated set of hardware Timers for each TCP/IP session or customizable for sharing stale sessions.
?Multiple 'slot storage' for fragmented packets. More slots allocated when more On-chip Memory available. Self-checking available memory logic. (optional)
?Out of sequence packet detection/storage and Reassembly/Segmentation (optional)
?RDMA- Direct Data placement in Applications buffer at full wire speed without CPU-> reduces CPU's buffer copy time and utilization by 95%
?Support VLAN Bypass mode (optional)
?Easily customizable for filtering various IP and TCP traffic Protocols, directed towards any port or IP(Ideal for security appliances)
?Implements Full TCP/IP offload or By-Pass mode. (Optional)
?Future Proof- Flexible implementation of TCP Offload
?Accommodates future Specifications changes.
?Basic mini API available for easy integration with Linux/windows. Others OSs/CPUs also available.
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