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| 供应商 | HDL Design House |
|---|---|
| 型号 | IEEE 1284 Parallel Port Controller |
| 类型 | Soft IP |
| 到期日 | Silicon proven |
| 源网址 | View more |
| 特征 | Performs host or peripheral operation modes Full hardware support for all data transfer modes Enables software handshake for initialization, protocol negotiation and data transfer phases Performs automatic data transfer in Compatible,Nibble, Byte, EPP, and ECP modes DMA capability in ECP mode of operation for fullspeeddata transfer Hardware support for Centronics and IEEE Compatible Busy_Strobe_Ack timing Provides fourteen architectural configuration registers Enables software configurability through CONFIG register Provides sixteen different interrupts |
| 详情页 | View more |
| 附件链接 | View more |
The PSPP1284 core implements the IEEE 1284 interface (parallel port). Software-programmable for the operation as a host or peripheral device, the core supports Compatible, Nibble, Byte, EPP, and ECP mode of operations and includes a configurable depth FIFO tightly coupled with the DMA engine for efficient data transfer in ECP mode. Full-speed data transfer can be performed by initializing the core in ECP operation mode with DMA transfer enabled, and waiting for an interrupt at completion. The core provides a solution for parallel ports that requires minimal software assistance. Using the PSPP1284, parallel port control and data lines can be accessed by the active core or directly by the CPU if the core isn't active. The PSPP1284 is designed to connect to any CPU through a generic bus interface, which can be modified to match any bus specification upon customer request. Fourteen architectural registers allow flexible software control of core configuration operation and data transfer. Sixteen different interrupts can be used for creating handshakes with software. This IP core has been designed and verified using Cadence state-of-the-art EDA tools, methodology and recommended design and verification flow.
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