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The I65GV25_DLL_01 is capable of generating 4-channel fixed timing delay and 1-channel test mode for DDR SDRAM controller's usage. The delay time is set to 20% of DQS periods, and the delayed outputs DQSD[4:1] are in concert with the reference input clock (FREF) for DQ data latch purpose. Regarding the architecture, this IP integrates a Voltage-Controlled Delay Line (VCDL), a Phase-Frequency Detector (PFD) and a Charge Pump (CP). With an operating voltage ranging from 0.9V ~ 1.1V, and junction temperature from -40? ~ 125?, it can process input clock frequencies from 100MHz ~ 200MHz.
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