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| 供应商 | HDL Design House |
|---|---|
| 型号 | Physical Coding Sublayer (PCS) IP Core |
| 类型 | Hard IP |
| 到期日 | Silicon proven |
| 源网址 | View more |
| 特征 | Highly configurable, more than 30 registers available Supports 8 Lanes in TX and 8 Lanes in RX path Lane misalignment of up to 8 octets is supported 8B10B encoding/decoding applied PRBS generation/verification support (both per Lane and per SF payload) Per Lane Loopback supported Various reference clock support for Ser/Des Lane's PLL Fully synchronous design |
| 详情页 | View more |
| 附件链接 | View more |
The Physical Coding Sublayer (PCS) IP Core enables transmission and reception of data via 8-Lanes SerDes interface. It is able to multiplex a synchronous digital stream of data over 8 Lanes, while guaranteeing data alignment and super-frame synchronization. The PCS is responsible for idle sequence generation, lane striping and encoding for transmission and decoding, lane alignment and restriping on reception. The PCS uses an 8B/10B encoding for transmission over the link. This IP core has been designed and verified using Cadence state-of-the-art EDA tools, methodology and recommended design and verification flow.
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