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| 供应商 | HDL Design House |
|---|---|
| 型号 | Serial RapidIO endpoint IP core |
| 类型 | Soft IP |
| 到期日 | Pre-silicon |
| 源网址 | View more |
| 特征 | Conforms to the RapidIO Interconnect Specification – Rev. 2.0.1 AMBA 3 AXI ARM CPU host interface, for high performance on-chip communication. Supports multiple high speed lanes, (1x, 2x, 4x, 8x and 16x modes) Configurable modes of operation; 1.25 Gbaud/s, 2.5 Gbaud/s, 3.125 Gbaud/s, 5Gbaud/s, 6.25Gbaud/s transfer rates Internal multi-channel DMA controller that fully exploits AXI protocol features and thus supports highest available data throughput and back to back packets transmission. Configuration and Status Register File containing over 40 architectural registers providing total software control of IP core. Number of software maskable interrupt request signals. Full backward compatibility with RapidIO specification revision 1.3 Provides roadmap to future RapidIO specification revisions. |
| 详情页 | View more |
| 附件名称 | HIP3300.pdf |
| 附件链接 | View more |
HIP 3300 Serial RapidIO endpoint IP core is compliant with RapidIO specification version 2.0.1. IP core is based on a generic, highly modular architecture from which a variety of solutions can be easily created to effectively and efficiently address customers' specific requirements. The HIP 3300 Serial RapidIO IP solution is a complete high-performance core that incorporates a logical layer, a transport layer, and a physical layer. HIP3300 IP core also supports I/O and message-passing. The core provides a Serial RapidIO interface on one side and ARM's AMBA 3 AXI, high performance interface on the other side of the core, allowing flexible and high performance communication with host CPU. Modular design of the IP core allows easy implementation of add-on third party bus interfaces and/or other standard bus interface. This IP core has been designed and verified using Cadence state-of-the-art EDA tools, methodology and recommended design and verification flow.
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